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NSF-NRI Graduate Student and Postdoctoral Fellow Supplements to NSF Centers in Nanoelectronics

Status: Archived

Archived funding opportunity

This document has been archived.

Important information for proposers

All proposals must be submitted in accordance with the requirements specified in this funding opportunity and in the NSF Proposal & Award Policies & Procedures Guide (PAPPG) that is in effect for the relevant due date to which the proposal is being submitted. It is the responsibility of the proposer to ensure that the proposal meets these requirements. Submitting a proposal prior to a specified deadline does not negate this requirement.


See the Dear Colleague Letter, NSF 10-031, announcing this opportunity at http://www.nsf.gov/publications/pub_summ.jsp?ods_key=nsf10031.

The National Science Foundation (NSF) has undertaken a cooperative effort with the Semiconductor Industry Association (SIA) through the industry's Nanoelectronics Research Initiative (NRI) to provide supplemental funding opportunities to NSF centers involved in long-term nanoelectronics research. The supplemental funding supports additional graduate students and postdoctoral fellows to work in collaborative efforts with participating NRI company assignees on exploring new concepts beyond the scaling limits of CMOS (Complementary Metal Oxide Semiconductor) technology. Such efforts are intended to enhance nanoelectronics research and education, strengthen industry linkages with NSF centers, and develop future cadres of industry and faculty researchers to help drive the field.

NSF and NRI are continuing this cooperative supplement opportunity for a fifth year. The supplement research topics must be consistent with the goals of the NSF centers and must also align with the goals of NRI to find a novel, non-FET based logic switch as a successor to CMOS technology. NRI is focused primarily on research on devices utilizing new computational state variables other than the control of electronic charge by a potential barrier utilized in current FET technology. For this supplement opportunity, NRI is particularly interested in three areas: Circuit architectures for doing computation with non-FET devices; directed self-assembly and bottoms-up fabrication of specific non-FET device structures; and nano-engineering of phonon flow in non-FET devices and circuits to control heat and enable non-equilibrium behavior.  Since the primary limitation to scaling is increasing power density, all of the non-FET devices and architectures should focus on opportunities for achieving low energy consumption while maintaining high computational speed, and NRI is open to new ideas in this area in general.

Recent awards made through this supplement activity may be found at http://www.nsf.gov/crssprgm/nano/


Program contacts

Lawrence S. Goldberg
lgoldber@nsf.gov (703)292-8339
Thomas P. Rieker
trieker@nsf.gov (703)292-4914
Sankar Basu
sabasu@nsf.gov (703)292-7843 CISE/CCF

Awards made through this program

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