NSF 12-556: FAILURE-RESISTANT SYSTEMS (FRS)

Program Solicitation NSF 12-556

		National Science Foundation Directorate for Computer & Information Science & Engineering      Division of Computing and Communication Foundations Directorate for Engineering      Division of Electrical, Communications and Cyber Systems
		Semiconductor Research Corporation

Full Proposal Deadline(s) (due by 5 p.m. proposer's local time):

     July 26, 2012

Important Information And Revision Notes

A revised version of the NSF Proposal & Award Policies & Procedures Guide (PAPPG), NSF 11-1, was issued on October 1, 2010 and is effective for proposals submitted, or due, on or after January 18, 2011. Please be advised that the guidelines contained in NSF 11-1 apply to proposals submitted in response to this funding opportunity.

Cost Sharing: The PAPPG has been revised to implement the National Science Board's recommendations regarding cost sharing. Inclusion of voluntary committed cost sharing is prohibited. In order to assess the scope of the project, all organizational resources necessary for the project must be described in the Facilities, Equipment and Other Resources section of the proposal. The description should be narrative in nature and must not include any quantifiable financial information. Mandatory cost sharing will only be required when explicitly authorized by the NSF Director. See the PAPP Guide Part I: Grant Proposal Guide (GPG) Chapter II.C.2.g(xi) for further information about the implementation of these recommendations.

Data Management Plan: The Proposal & Award Policies & Procedures Guide (PAPPG) contains a clarification of NSF's long standing data policy. All proposals must describe plans for data management and sharing of the products of research, or assert the absence of the need for such plans. FastLane will not permit submission of a proposal that is missing a Data Management Plan. The Data Management Plan will be reviewed as part of the intellectual merit or broader impacts of the proposal, or both, as appropriate. Links to data management requirements and plans relevant to specific Directorates, Offices, Divisions, Programs, or other NSF units are available on the NSF website at: https://www.nsf.gov/bfa/dias/policy/dmp.jsp. See Chapter II.C.2.j of the Grant Proposal Guide (GPG) for further information about the implementation of this requirement.

Postdoctoral Researcher Mentoring Plan: A proposal that requests funding to support postdoctoral researchers must include, as a supplementary document, a description of the mentoring activities that will be provided for such individuals. Please be advised that if required, FastLane will not permit submission of a proposal that is missing a Postdoctoral Researcher Mentoring Plan. See Chapter II.C.2.j of the Grant Proposal Guide (GPG) for further information about the implementation of this requirement.

Summary Of Program Requirements

General Information

Program Title:

FAILURE-RESISTANT SYSTEMS (FRS)
A Joint Initiative between NSF and SRC

Synopsis of Program:

The National Science Foundation (NSF) and the Semiconductor Research Corporation (SRC) have agreed to embark on a new collaborative research program to address compelling research challenges in failure resistant systems that are of paramount importance to industry, academia, and society at large.

New approaches in the design of electronic circuits and systems are needed for products and services that continue to operate correctly in the presence of transient, permanent, or systematic failures. From large information processing systems supporting communications and computation, to small embedded systems targeting medical and automotive applications, whole industries are facing the challenge of improving the reliability of systems.

Increasing miniaturization and integrated circuit fabrication processes are creating a tension between reliability and efficiency. Higher rates of faults, variation, and degradation due to aging in integrated circuits are forcing systems engineers to assume that devices and circuits may not always perform as designed. More and more, systems are constructed using IP blocks (3rd party Intellectual Property) from different sources, contributing further to unpredictable behavior. Thus behavior under adverse conditions may not be fully known in deployed systems. Current techniques for ensuring reliability, such as voltage and clock rate margins, replication, and disk-based check-pointing will not be able to satisfy the competing requirements for future integrated circuits. These techniques typically operate only at one level of the system stack, yet layers from devices to applications all contribute to system reliability. Such single-layer techniques must be used under worst-case assumptions about the other layers in the stack. This potentially leads to inefficiencies that will make these techniques impractical in future fabrication processes.

A system-level cross-layer approach to reliability, encompassing failure mechanisms of both digital and analog components, has the potential to deliver high reliability with significantly lower power and performance overheads than current single-layer techniques. By distributing reliability across the system design stack, cross-layer approaches can take advantage of the information available at each level, including even application-level knowledge, to efficiently tolerate errors, aging, and variation. This will allow handling of different physical effects at the most efficient stack layer, and can be adapted to varying application needs, operating environments, and changing hardware state.

Fundamental new advances in techniques for designing and developing systems resilient to failure could have a significant impact on multiple industries and boost their competitiveness on a global scale, helping to transform market segments and translate research results into practice.

Cognizant Program Officer(s):

Please note that the following information is current at the time of publishing. See program website for any updates to the points of contact.

• Sankar Basu, CISE/CCF Program Director, 1115, telephone: (703) 292-7843, email: sabasu@nsf.gov

• Ahmed Louri, CISE/CCF Program Director, 1115, telephone: (703) 292-8238, email: alouri@nsf.gov

• George Haddad, ENG/ECCS Program Director, 525, telephone: (703) 292-8897, email: ghaddad@nsf.gov

• Anupama B. Kaul, ENG/ECCS Program Director, 525, telephone: (703) 292-8153, email: akaul@nsf.gov

• William Joyner, Director/CADTS, SRC, telephone: (919) 941-9472, email: william.joyner@src.org

• David Yeh, Director/ICSS, SRC, telephone: (919) 941-9464, email: David.Yeh@src.org

Applicable Catalog of Federal Domestic Assistance (CFDA) Number(s):

• 47.041 --- Engineering
• 47.070 --- Computer and Information Science and Engineering

Award Information

Anticipated Type of Award: Standard Grant or Continuing Grant

Estimated Number of Awards: 15 to 20 awards, each ranging from $300,000 to $400,000 over three years, will be made, pending availability of funds.

Anticipated Funding Amount: $6,000,000 of which $3,600,000 will be contributed by NSF over a period of 3 years, and $2,400,000 will be contributed by SRC over a period of 3 years, pending availability of funds.

Eligibility Information

Organization Limit:

Proposals may only be submitted by the following:

• Universities and Colleges - Universities and two- and four-year colleges (including community colleges) accredited in, and having a campus located in the US, acting on behalf of their faculty members. Such organizations also are referred to as academic institutions.

PI Limit:

None Specified

Limit on Number of Proposals per Organization:

None Specified

Limit on Number of Proposals per PI: 1

An individual may participate in at most one proposal as PI, coPI, or senior personnel.

Proposal Preparation and Submission Instructions

A. Proposal Preparation Instructions

• Letters of Intent: Not Applicable

• Preliminary Proposal Submission: Not Applicable

• Full Proposals:
  • Full Proposals submitted via FastLane: NSF Proposal and Award Policies and Procedures Guide, Part I: Grant Proposal Guide (GPG) Guidelines apply. The complete text of the GPG is available electronically on the NSF website at: https://www.nsf.gov/publications/pub_summ.jsp?ods_key=gpg.
  • Full Proposals submitted via Grants.gov: NSF Grants.gov Application Guide: A Guide for the Preparation and Submission of NSF Applications via Grants.gov Guidelines apply (Note: The NSF Grants.gov Application Guide is available on the Grants.gov website and on the NSF website at: https://www.nsf.gov/publications/pub_summ.jsp?ods_key=grantsgovguide)

B. Budgetary Information

• Cost Sharing Requirements: Inclusion of voluntary committed cost sharing is prohibited.

• Indirect Cost (F&A) Limitations: Not Applicable

• Other Budgetary Limitations: Not Applicable

C. Due Dates

• Full Proposal Deadline(s) (due by 5 p.m. proposer's local time):

       July 26, 2012

Proposal Review Information Criteria

Merit Review Criteria: National Science Board approved criteria apply.

Award Administration Information

Award Conditions: Additional award conditions apply. Please see the full text of this solicitation for further information.

Reporting Requirements: Additional reporting requirements apply. Please see the full text of this solicitation for further information.

Agency Contacts

Other Information

I. Introduction

The National Science Foundation (NSF), through its Divisions of Computing and Communication Foundations (CCF) and Electrical, Communications and Cyber Systems (ECCS), has established a partnership with the Semiconductor Research Corporation (SRC), through its Computer-Aided Design and Test Sciences (CADTS) and Integrated Circuits and Systems Sciences (ICSS) areas, to jointly support innovative research activities focused on failure-resistant system design.

One cause of reduced reliability of electronic computing systems is the increasing probability of device failure as feature sizes of integrated circuits are reduced. For example, in energy efficient electronic systems, the switching energies per switching event in nano-scale transistors may be so low that transistors are more susceptible to background noise arising from thermal fluctuations. This may be a source of erroneous switching and hence poses a reliability concern at the device level. Also, due to progressive miniaturization significant variations in transistor characteristics may arise in the fabrication processes. With increased presence of analog circuits and components as parts of systems as well as increased 3D integration density, further reliability concerns arise beyond reduced device reliability and increased parameter uncertainty. The coupling between densely integrated components, circuits, packaging, and sub-systems is often too complex to be fully considered in the design. Thus, failure might be caused by either design errors (or poor designs) or operational conditions. "Failure" of such systems may be defined in a more subtle manner than just the traditional "pass/fail." For many systems, designers will be concerned with graceful degradation at the application level, recovery from transient and permanent errors, and robust behavior at the system level. This suggests that an integrated approach incorporating all levels of the design hierarchy is necessary to provide reliability to the system user. Furthermore, this cross layer approach is apparent in multiple application spaces, including high performance computing and communications, electronics for aerospace and other transportation systems, and healthcare applications. To meet these application requirements, reliability needs to encompass digital, analog, and RF design across a wide range of operating conditions as well as a variety of failure modes.

Proposals in three broad categories are solicited. These are Resilient System Architectures, Modeling of Cross-layer Reliable Systems, and Tools and Automation for Failure-Resistant System Design. Further details on the three categories are described in the program description.

Proposals need not address all aspects of the resiliency challenge, and it is expected that proposals submitted in response to this solicitation be set in one or more of the following overlapping contexts: (1) prediction, i.e., failure modeling at design time and/or at run-time; (2) detection of failures; (3) containment or limiting the impact of failures; (4) correction of incorrect results; (5) diagnosis of the specific portions of the system that are malfunctioning; and (6) repair of the system to make it function correctly afterwards.

II. Program Description

Proposals are solicited for foundational and transforming research into architectures, modeling, tools, techniques, and metrics for cross-layer approaches to reliability. While a comprehensive attack on reliability needs to address problems all the way from devices, through circuits and micro-architectures, to operating systems, middleware and application layer software, this particular solicitation will focus on the hardware aspects and on software techniques that directly interact with hardware.

Specifically excluded are application software and other software approaches that do not emphasize the impact upon the hardware. Within this intellectual framework proposals submitted in response to this solicitation are expected to address at least one of the following three categories.

1. Resilient system architectures

We seek projects exploring new architectures and supporting implementations. Specific topics may include:

Interfaces for multi-level cooperation: Abstractions that hide unnecessary details from other layers of the (hardware) stack while communicating critical information (up and down the stack) about reliability and errors; interfaces that allow software to communicate reliability needs, types of errors that can be tolerated, invariants that should hold under correct operation, and capabilities for managing errors to hardware; and techniques that allow hardware to communicate its state to software without requiring that the software understand the details of the hardware design.

Self-repairing and self-testing systems: Techniques to diagnose changing system state over time; interfaces to expose and control reconfiguration across stack layer boundaries; and architectures that support repair by isolating defective components and eliminating single-points-of-failure. Formal/accurate specification for consistent tolerant behavior requirements at each layer with respect to the overall cross layer resiliency to enable design optimization and evaluation of each layer and interfaces between layers. Recovery features (firmware, architecture, circuits etc.) based on transient or permanent failures either to enable re-execution or to re-map execution to alternative healthy resources.

Differential reliability: Techniques that allow a single chip or system to operate at a wide range of points on the efficiency/reliability tradeoff curve. Failure recovery and repair mechanisms to adapt gracefully to transient, permanent, and systematic failures while allowing for alternate means to provide safety-critical functionality.

Scalable adaptive reliability: Adaptation to environment and system state; approaches that allow systems to tailor their reliability to the constraints imposed by different operating environments and changing system state so they deliver the highest possible performance and energy efficiency at all times and in all locations.

In-field techniques: Techniques for in-field self-adjustments to temporal variations such as temperature changes, voltage fluctuations, and aging, in order to remove the need for "worst-case" voltage and frequency guard-bands in design. Successful techniques may involve reconfigurable hardware and provide such adaptation at minimal cost of energy and performance by exploiting cross-layer capabilities and features.

Checkpointing: Techniques that exploit application characteristics to reduce checkpoint overhead by checkpointing at the most efficient times and exploiting tradeoffs between the amount of data that must be stored in a checkpoint and the amount of work required to recover from the checkpoint. Optimal distribution of responsibility for checking assertions across different layers of the stack could also be a topic of proposed research.

Graceful degradation and adaptation: This requirement demands that the system be aware of the health of its components and able to use that information to understand its overall health and capacity. Of particular interest are approaches that allow systems to adapt to provide the best possible performance, reliability, and quality of service in the face of changing (often degrading) system capabilities; techniques that express an application's sensitivity to parallelism, clock rate, I/O standard restrictions, etc., so that the system can optimize for performance and/or energy are also of interest. Also of interest are methodologies for exploring capacity/quality tradeoffs via communicating or exposing capacity and quality parameters.

Side-channel or debug interface: techniques that allow remote diagnosis and recovery, especially for events in which resiliency problems affect system operation.

2. Modeling of cross-layer reliable systems

We seek projects to identify and understand models of failure mechanisms and the requirements of application domains including, but not limited to high performance computing and communications, electronics for aerospace and other transportation systems, and health care applications. Accurate and efficient simulation and modeling capabilities will be needed at all levels of abstraction including devices, circuits, systems and applications. Specific topis may include:

Models, metrics and benchmarks for cross-layer reliable system design: Techniques to evaluate the effectiveness of reliability schemes, characterize costs, and guide design and optimization.

Multi-level error filtering: Methods for modeling and communicating types and rates of errors that each level can handle; approaches that allow systems to dynamically select which level of the stack handles a given type of error; modeling tools to evaluate the costs of filtering different types of errors at different levels of the stack.

Identification and characterization: Modeling of failure mechanisms of digital, analog, and passive components, as well as those of embedded IP blocks; these techniques must be capable of taking into account the best methods and models of variation for first pass success in the design of analog and embedded IP blocks. Use of modeling, measurement, or simulation techniques to obtain reliable estimates on the actual probabilities of common cause failures.

Early detection: Quantification of degradation mechanisms and models of degradation for the system in the field to enable both preventive measures and subsequently deployed adaptation strategies; such techniques may include modeling of runtime failures and associated runtime failure avoidance strategies.

Formal reliability specification: High-level modeling methodologies that formally define reliability specifications, and enables synthesis of reliability requirements based on design tradeoffs and failure prediction; methods and criteria to automatically select pre-silicon collateral (modules, libraries, design styles, architectures, etc.) that can be translated to silicon or used as guidance.

3. Tools and automation for failure-resistant system design

Cross-layer design tools and uncertainty simulation and analysis tools for analog and mixed-signal systems as well as digital systems are needed in order to evaluate the potential for a given design to suffer from reliability problems arising from uncertainties, and to decide which reliability enhancement tools must be employed, if any. Specifically, tools are needed to generate descriptions for uncertainties in physical parameters, geometrical parameters and noise parameters, and subsequently to propagate these parameters to descriptions of electrical parameters. Tools to generate variability- and noise-aware stochastic macro-models to enable system level optimization and synthesis of sensitive circuit blocks of mixed signal systems may also be needed . Specific topics may include:

Verification of system reliability: Both pre-silicon and post-silicon verification of system reliability in the presence of faults; analysis capabilities to provide for global optimization, particularly using cross-layer information; tools to verify fault-tolerance features of circuits by providing directed simulation stimuli to simulations of fault identification and recovery.

Multi-objective optimization: Methods and tools for multi-objective optimization to account for the effects of unreliability and degradation on performance and on the area and power costs of over-provisioning.

Scalability: Tools and techniques for distributed simulation of extremely large systems with heterogeneous processor architectures consisting of potentially hundreds of cores, including techniques for error injection and monitoring of fault detection and recovery.

Multi-layer testing: Tools for checking system reliability at time zero as well as over time and in the field; testing techniques that could determine how a system's current set of faults and/or aging has affected its ability to tolerate future faults and aging in order to estimate "expected remaining lifetime" (as opposed to simple pass/fail techniques); efficient testing strategies for resilient (adaptive, non-deterministic) systems with time-bounded confirm/reject characteristics in a manufacturing environment.

Tools and automation for cross-layer reliable design: Simulators, modeling frameworks, and optimization tools for overall reliability analysis; synthesis of novel reliable-by-construction design at different levels of abstraction; design optimization for reliability, power, performance, and area; automated resiliency integration tools; tools to propagate and quantify the effects of manufacturing uncertainties on system level reliability.

Pinpointing failure-prone areas: Tools and techniques to identify areas in a design that are prone to reliability failures, to determine the failure modes, and to provide suggestions on fault-tolerance solutions; automated insertion of reliability features based on user-defined tradeoffs with area/power requirements; techniques to estimate the quality of reliability features.

III. Award Information

Each project will be jointly funded by the NSF and the SRC through separate NSF and SRC funding instruments. For each project, NSF support will be provided via an NSF grant and SRC support will be provided via a SRC contract. Depending upon the nature of the project, the total of the NSF grant plus SRC contract will range from a total of $300,000 to $400,000 over 3 years. It is anticipated that approximately 15-20 projects will be supported, pending the availability of funds.

IV. Eligibility Information

Organization Limit:

Proposals may only be submitted by the following:

• Universities and Colleges - Universities and two- and four-year colleges (including community colleges) accredited in, and having a campus located in the US, acting on behalf of their faculty members. Such organizations also are referred to as academic institutions.

PI Limit:

None Specified

Limit on Number of Proposals per Organization:

None Specified

Limit on Number of Proposals per PI: 1

An individual may participate in at most one proposal as PI, coPI, or senior personnel.

V. Proposal Preparation And Submission Instructions

A. Proposal Preparation Instructions

Full Proposal Preparation Instructions: Proposers may opt to submit proposals in response to this Program Solicitation via Grants.gov or via the NSF FastLane system.

• Full proposals submitted via FastLane: Proposals submitted in response to this program solicitation should be prepared and submitted in accordance with the general guidelines contained in the NSF Grant Proposal Guide (GPG). The complete text of the GPG is available electronically on the NSF website at: https://www.nsf.gov/publications/pub_summ.jsp?ods_key=gpg. Paper copies of the GPG may be obtained from the NSF Publications Clearinghouse, telephone (703) 292-7827 or by e-mail from nsfpubs@nsf.gov. Proposers are reminded to identify this program solicitation number in the program solicitation block on the NSF Cover Sheet For Proposal to the National Science Foundation. Compliance with this requirement is critical to determining the relevant proposal processing guidelines. Failure to submit this information may delay processing.

• Full proposals submitted via Grants.gov: Proposals submitted in response to this program solicitation via Grants.gov should be prepared and submitted in accordance with the NSF Grants.gov Application Guide: A Guide for the Preparation and Submission of NSF Applications via Grants.gov. The complete text of the NSF Grants.gov Application Guide is available on the Grants.gov website and on the NSF website at: (https://www.nsf.gov/publications/pub_summ.jsp?ods_key=grantsgovguide). To obtain copies of the Application Guide and Application Forms Package, click on the Apply tab on the Grants.gov site, then click on the Apply Step 1: Download a Grant Application Package and Application Instructions link and enter the funding opportunity number, (the program solicitation number without the NSF prefix) and press the Download Package button. Paper copies of the Grants.gov Application Guide also may be obtained from the NSF Publications Clearinghouse, telephone (703) 292-7827 or by e-mail from nsfpubs@nsf.gov.

In determining which method to utilize in the electronic preparation and submission of the proposal, please note the following:

Collaborative Proposals. All collaborative proposals submitted as separate submissions from multiple organizations must be submitted via the NSF FastLane system. Chapter II, Section D.4 of the Grant Proposal Guide provides additional information on collaborative proposals.

Budget:

Grantees of this program will be expected to attend, and shall budget for, annual SRC grantee review meetings for the purpose of sharing research progress with SRC member company representatives as well as other interested individuals. The first such meeting will be held approximately nine months after the awards are made, and succeeding meetings will be held every 12 months thereafter.

Supplementary Docs:

In order to be considered for funding in this program, every proposal MUST include a statement of consent from the proposing institution(s) that indicates that NSF may share the proposal, reviews generated for the proposal, and related information, with SRC. The statement of consent must be uploaded into the Supplementary Docs section in Fastlane or Grants.gov. Proposals that do not contain this statement will be returned without review.

For proposals involving academic institutions and industry, proposers should include a letter from the industrial partner(s) that confirm(s) the participation of one or more co-PIs from industry. This letter, uploaded in the Supplementary Documents section in FastLane or Grants.gov, should describe a plan for interaction between the industrial and academic partners, the time commitment of the industrial researcher(s), and the nature of the work.

B. Budgetary Information

Cost Sharing: Inclusion of voluntary committed cost sharing is prohibited

Budget Preparation Instructions:

Researchers from foreign academic institutions who contribute essential expertise to the project may participate as co-PIs or senior personnel but may not request NSF or SRC support. Synergistic collaborations or partnerships with industry or government are allowed when appropriate, though no NSF or SRC funds will be provided to these organizations.

C. Due Dates

• Full Proposal Deadline(s) (due by 5 p.m. proposer's local time):

       July 26, 2012

D. FastLane/Grants.gov Requirements

• For Proposals Submitted Via FastLane:

  Detailed technical instructions regarding the technical aspects of preparation and submission via FastLane are available at: https://www.fastlane.nsf.gov/a1/newstan.htm. For FastLane user support, call the FastLane Help Desk at 1-800-673-6188 or e-mail fastlane@nsf.gov. The FastLane Help Desk answers general technical questions related to the use of the FastLane system. Specific questions related to this program solicitation should be referred to the NSF program staff contact(s) listed in Section VIII of this funding opportunity.

  Submission of Electronically Signed Cover Sheets. The Authorized Organizational Representative (AOR) must electronically sign the proposal Cover Sheet to submit the required proposal certifications (see Chapter II, Section C of the Grant Proposal Guide for a listing of the certifications). The AOR must provide the required electronic certifications within five working days following the electronic submission of the proposal. Further instructions regarding this process are available on the FastLane Website at: https://www.fastlane.nsf.gov/fastlane.jsp.

• For Proposals Submitted Via Grants.gov:

Before using Grants.gov for the first time, each organization must register to create an institutional profile. Once registered, the applicant's organization can then apply for any federal grant on the Grants.gov website. Comprehensive information about using Grants.gov is available on the Grants.gov Applicant Resources webpage: http://www07.grants.gov/applicants/app_help_reso.jsp. In addition, the NSF Grants.gov Application Guide provides additional technical guidance regarding preparation of proposals via Grants.gov. For Grants.gov user support, contact the Grants.gov Contact Center at 1-800-518-4726 or by email: support@grants.gov. The Grants.gov Contact Center answers general technical questions related to the use of Grants.gov. Specific questions related to this program solicitation should be referred to the NSF program staff contact(s) listed in Section VIII of this solicitation.

Submitting the Proposal: Once all documents have been completed, the Authorized Organizational Representative (AOR) must submit the application to Grants.gov and verify the desired funding opportunity and agency to which the application is submitted. The AOR must then sign and submit the application to Grants.gov. The completed application will be transferred to the NSF FastLane system for further processing.

VI. NSF Proposal Processing And Review Procedures

Proposals received by NSF are assigned to the appropriate NSF program where they will be reviewed if they meet NSF proposal preparation requirements. All proposals are carefully reviewed by a scientist, engineer, or educator serving as an NSF Program Officer, and usually by three to ten other persons outside NSF who are experts in the particular fields represented by the proposal. These reviewers are selected by Program Officers charged with the oversight of the review process. Proposers are invited to suggest names of persons they believe are especially well qualified to review the proposal and/or persons they would prefer not review the proposal. These suggestions may serve as one source in the reviewer selection process at the Program Officer's discretion. Submission of such names, however, is optional. Care is taken to ensure that reviewers have no conflicts of interest with the proposal.

A. NSF Merit Review Criteria

All NSF proposals are evaluated through use of the two National Science Board (NSB)-approved merit review criteria: intellectual merit and the broader impacts of the proposed effort. In some instances, however, NSF will employ additional criteria as required to highlight the specific objectives of certain programs and activities.

The two NSB-approved merit review criteria are listed below. The criteria include considerations that help define them. These considerations are suggestions and not all will apply to any given proposal. While proposers must address both merit review criteria, reviewers will be asked to address only those considerations that are relevant to the proposal being considered and for which the reviewer is qualified to make judgments.

What is the intellectual merit of the proposed activity?
How important is the proposed activity to advancing knowledge and understanding within its own field or across different fields? How well qualified is the proposer (individual or team) to conduct the project? (If appropriate, the reviewer will comment on the quality of the prior work.) To what extent does the proposed activity suggest and explore creative, original, or potentially transformative concepts? How well conceived and organized is the proposed activity? Is there sufficient access to resources?

What are the broader impacts of the proposed activity?
How well does the activity advance discovery and understanding while promoting teaching, training, and learning? How well does the proposed activity broaden the participation of underrepresented groups (e.g., gender, ethnicity, disability, geographic, etc.)? To what extent will it enhance the infrastructure for research and education, such as facilities, instrumentation, networks, and partnerships? Will the results be disseminated broadly to enhance scientific and technological understanding? What may be the benefits of the proposed activity to society?

Examples illustrating activities likely to demonstrate broader impacts are available electronically on the NSF website at: https://www.nsf.gov/pubs/gpg/broaderimpacts.pdf.

Mentoring activities provided to postdoctoral researchers supported on the project, as described in a one-page supplementary document, will be evaluated under the Broader Impacts criterion.

NSF staff also will give careful consideration to the following in making funding decisions:

Integration of Research and Education
One of the principal strategies in support of NSF's goals is to foster integration of research and education through the programs, projects, and activities it supports at academic and research institutions. These institutions provide abundant opportunities where individuals may concurrently assume responsibilities as researchers, educators, and students and where all can engage in joint efforts that infuse education with the excitement of discovery and enrich research through the diversity of learning perspectives.