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NSF/Intel Partnership on Foundational Microarchitecture Research

Status: Archived

Archived funding opportunity

This document has been archived.

Important information for proposers

All proposals must be submitted in accordance with the requirements specified in this funding opportunity and in the NSF Proposal & Award Policies & Procedures Guide (PAPPG) that is in effect for the relevant due date to which the proposal is being submitted. It is the responsibility of the proposer to ensure that the proposal meets these requirements. Submitting a proposal prior to a specified deadline does not negate this requirement.

Synopsis

The confluence of transistor scaling, increases in the number of architecture designs per process generation, the slowing of clock frequency growth, and recent success in research exploiting thread-level parallelism (TLP) and data-level parallelism (DLP) all point to an increasing opportunity for innovative microarchitecture techniques and methodologies in delivering performance growth in the future.

The NSF/Intel Partnership on Foundational Microarchitecture Research will support transformative microarchitecture research targeting improvements in instructions per cycle (IPC). This solicitation seeks microarchitecture technique innovations beyond simplistic, incremental scaling of existing microarchitectural structures. Specifically, FoMR seeks to advance research that has the following characteristics: (1) high IPC techniques ranging from microarchitecture to code generation; (2) “microarchitecture turbo” techniques that marshal chip resources and system memory bandwidth to accelerate sequential or single-threaded programs; and (3) techniques to support efficient compiler code generation. Advances in these areas promise to provide significant performance improvements that continue the trends characterized by Moore’s Law.  

 

 

Program contacts

Yuanyuan Yang
Program Director, CCF
yyang@nsf.gov (703) 292-8910
Jeff Parkhurst
Center Program Director
jeff.parkhurst@intel.com (916) 356-2508 Intel Labs
Sreenivas Subramoney
Center Managing Sponsor, Sr. Principal Engineer
sreenivas.subramoney@intel.com +91 98450 93277 Intel Labs

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