Enabling Access to the Semiconductor Chip Ecosystem for Design, Fabrication, and Training (Chip Design Hub)

Integrated micro/nano-electronic circuits (ICs) are a foundational technology that enable advancements in artificial intelligence, 5G/6G communication, security, scientific computing, quantum computing, and more. The economic competitiveness, technological leadership, and national security of the United States depend on a future workforce at the forefront of IC design and fabrication, spanning IC researchers, IC designers, and IC fabrication engineers and technicians. Since IC design and fabrication must deal with staggering complexities to meet system functionality, performance, and energy objectives, offering students at all levels with hands-on experiences designing and fabricating IC chips is imperative.

The needs of research and education communities in this domain have been widely recognized by a range of reports, including those derived from NSF-sponsored workshops. Prospective PIs for this solicitation are encouraged to read the following reports:

• NSF Workshop on Micro/Nano Circuits and Systems Design and Design Automation: Challenges and Opportunities (https://nsfedaworkshop.nd.edu/assets/432289/nsf20_eda_workshop_report.pdf)
• NSF Integrated Circuit Research, Education and Workforce Development Workshop (https://nsf-ic-education.com/NSF_IC_Workshop_Final_Report.pdf)
• NSF Workshop on CMOS+X Technologies (https://e3s-center.berkeley.edu/nsf-workshop-cmosx/cmos-x-report/)

In response to the urgent need for chip fabrication support in the academic community, NSF has invested in several new funding opportunities (e.g., Supplements for Access to Semiconductor Fabrication (ASF, https://new.nsf.gov/funding/opportunities/supplements-access-semiconductor-fabrication-asf), Partnership for Prototyping of CMOS+X Systems (CMOS+X, https://www.nsf.gov/pubs/2022/nsf22076/nsf22076.jsp). Advanced Chip Engineering Design and Fabrication (ACED Fab, https://new.nsf.gov/funding/opportunities/advanced-chip-engineering-design-fabrication-aced). While these investments support chip fabrication by academic researchers, they do not address end-to-end semiconductor chip design. This solicitation fills that gap. 

The aim of this solicitation is (i) to dramatically lower the barriers to accessing state-of-the-art electronic design automation (EDA) tools, process design kits (PDKs), and design intellectual property (IP) cores for students and academic researchers, and (ii) to enable students at various levels to design IC chips. A key goal is to broaden participation in IC chip design beyond the small number of institutions currently engaged in these activities.

This solicitation seeks proposals to establish and manage a community infrastructure that supports the entire IC chip design process beginning from behavior/structural description at the Register Transfer Level (RTL) or above to GDSII fabrication mask file generation. The infrastructure should provide licensing, access, and maintenance of (i) commercial and/or open-source EDA tools necessary for the end-to-end IC chip design and verification process, and (ii) design PDK/IPs at various CMOS technology nodes (potentially including emerging technologies), as well as support for multi-project-chip (MPC) integration. Further, proposals should include efforts to develop, curate, and host educational/tutorial materials on the entire IC chip design flow to help train the next generation of IC designers and researchers.

PIs interested in submitting a proposal to this program are strongly encouraged to discuss their plans with cognizant Program Officers.